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[VHDL-FPGA-Verilog] flowled

Description: FPGA开发入门的Verilog HDL程序---流水灯,真实可用，验证通过，工程环境为Altera Quartus -FPGA development of Verilog HDL entry procedures- water lights, the real available, authentication is passed, the project environment for Altera Quartus
Platform: | Size: 193536 | Author: renyong0801 | Hits:

[VHDL-FPGA-Verilog] liangzhu

Description: FPGA开发入门的Verilog HDL程序2---梁祝音乐播放,真实可用，验证通过，工程环境为Altera Quartus II -Introduction to the Verilog HDL FPGA development process 2 --- Butterfly music player, the real available, verified by the project environment for the Altera Quartus II
Platform: | Size: 301056 | Author: renyong0801 | Hits:

[Other] traffic

Description: 交通灯控制系统的FPGA设计与实现，红灯亮55s，黄灯亮5s，绿灯亮50s-Traffic Light Control System Design and Implementation of FPGA, the red light 55s, yellow light 5s, green 50s
Platform: | Size: 364544 | Author: liujia | Hits:

[Other] bu_jin_kong_zhi

Description: 步进电机位置控制系统的FPGA设计与实现。-Stepping Motor Position Control System Design and Implementation of FPGA.
Platform: | Size: 1479680 | Author: liujia | Hits:

[Other] zhi_liu_dian_ji_kong_zhi

Description: 直流电动机控制系统的FPGA的设计与实现。-DC Motor Control System Design and Implementation of FPGA.
Platform: | Size: 1432576 | Author: liujia | Hits:

[VHDL-FPGA-Verilog] asyn_FIFOandFPGAdesign

Description: 一篇关于FIFO设计以及FPGA设计的文章-FIFO 1 on the design and FPGA design article
Platform: | Size: 453632 | Author: Roger | Hits:

[VHDL-FPGA-Verilog] trafficlight_design_based_on_fpga

Description: 基于FPGA的交通灯的设计 有Verilog HDL 源码、仿真图与引脚配置图，已下载实现 -FPGA-based design of traffic lights have Verilog HDL source code, simulation map with pin configuration map has been downloaded realize
Platform: | Size: 408576 | Author: | Hits:

[Other] fpga_mac_vhdl

Description: 针对嵌入式系统的底层网络接口给出了一种由FPGA实现的以太网控制器的设计方法．该控制器能支持10Mbps和100Mbps的传输速率以及半双工和全双工模式，同时可提供MII接口，可并通过外接以太网物理层（PHY）芯片来实现网络接入 -Embedded systems for the bottom of this paper, a network interface from FPGA to achieve the Ethernet controller design method. The controller will support the 10Mbps and 100Mbps transfer rate, as well as half-duplex and full-duplex mode, at the same time provides MII interface, and through external Ethernet physical layer (PHY) chip to achieve network access
Platform: | Size: 316416 | Author: 林大朋 | Hits:

[VHDL-FPGA-Verilog] SVPWM

Description: 这是一个对电机进行SVPWM调速控制的VHDL源代码程序,包括了rtl主程序和测试sim仿真程序-This is a motor SVPWM Speed VHDL source code control procedures, including the main program and test rtl simulation program sim
Platform: | Size: 13312 | Author: 杨国超 | Hits:

[VHDL-FPGA-Verilog] fpgajpeg

Description: 基于FPGA的JPEG图像压缩芯片设计 -FPGA-based JPEG image compression chip design
Platform: | Size: 103424 | Author: 倪德 | Hits:

[VHDL-FPGA-Verilog] passlock

Description: 基于FPGA的电子密码锁的设计，内有Verilog HDL源码和各仿真图像-FPGA-based design of electronic locks, which have Verilog HDL source code and the simulation image
Platform: | Size: 532480 | Author: | Hits:

[VHDL-FPGA-Verilog] keyq

Description: 用FPGA 是先键盘的程序，is good for you -FPGA is the first keyboard to use the procedure, is good for you
Platform: | Size: 1024 | Author: fei | Hits:

[MiddleWare] arm

Description: 一个FPGA 测试例子,可以直接调试I/O口-A FPGA test examples can be directly debug I/O port
Platform: | Size: 86016 | Author: awney | Hits:

[VHDL-FPGA-Verilog] UART

Description: 在ＶＨＤＬ上编写了UART通信协议，对于ＦＰＧＡ开发有很大帮助-In VHDL on the preparation of a UART communication protocol, for FPGA development of great help
Platform: | Size: 143360 | Author: 王忠 | Hits:

[VHDL-FPGA-Verilog] DCT_IDCT

Description: 离散余弦变换及反离散余弦变换的HDL代码及测试文件。包括VHDL及Verilog版本。可用途JPEG及MEPG压缩算法。-Discrete cosine transform and inverse discrete cosine transform of the HDL code and test files. Including VHDL and Verilog versions. And MEPG can use JPEG compression algorithm.
Platform: | Size: 29696 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] huffman

Description: 用于FPGA的huffman算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-The huffman algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Platform: | Size: 10240 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] quant

Description: 用于FPGA的量化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-Quantitative algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Platform: | Size: 14336 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] rle

Description: 用于FPGA的变长编码算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-Variable-length encoding for FPGA HDL coding algorithms, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Platform: | Size: 4096 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] zigzag

Description: 用于FPGA的Z变化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-脫脙脫脷FPGA渭脛Z 卤 盲 禄炉 脣茫 篓 渭脛HDL 卤 脿脗毛 拢 卢 掳 眉脌 篓 VHDL 录 掳 Verilog
Platform: | Size: 7168 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] zigzag_decode

Description: 用于FPGA的反Z变换算法的Verilog代码。可用于JPEG及MPEG压缩算法。-FPGA for the anti-Z transform algorithm of Verilog code. Can be used in JPEG and MPEG compression algorithms.
Platform: | Size: 3072 | Author: caesar | Hits:
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